1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device which includes a metal gate having a low resistance and a method of manufacturing the same.
2. Description of the Prior Art
Recently, as a design rule for Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) devices have been rapidly decreased to a level less than a sub-100 nm class, RC delay of a gate, i.e. a word-line, has become an important issue. Therefore, in order to solve the RC delay of the word-line, application of gate material with a lower resistivity has been attempted as an alternative plane. Specifically, a metal gate structure formed from stacked layers of a polysilicon layer and a metal layer is used as the gate material, instead of a polysicide gate structure formed from stacked layers of a polysilicon layer and a metal silicide layer. Recently, for example, the application of tungsten gate in which tungsten is used as a metal layer has been actively researched.
Further, as a channel length becomes shorter due to the high integration of the MOSFET devices, the occurrence of defect in the MOSFET devices is increasing due to the short channel effect. A recess gate in which a recess is formed as a gate on a portion of a semiconductor substrate in manufacturing a transistor is being actively researched and developed. According to such a recess gate structure, the channel length can be increased by forming the gate in the recess, thereby remarkably decreasing the occurrence of defects due to the short channel effect, in comparison with the conventional planar gate structure.
Hereinafter, a method of manufacturing a semiconductor device having a tungsten gate, which is currently used, will be described in brief with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a isolation layer 2 defining an active region is formed on a semiconductor substrate 1. Next, after a gate insulation layer 3 is formed in the active region defined by the isolation layer 2 in a gate oxidation process, a polysilicon layer 4, a tungsten nitride layer 5 and a tungsten layer 6 are sequentially formed as a gate conductive layer on the gate insulation layer 3 including the isolation layer 2.
Referring to FIG. 1B, after a nitride layer is deposited on the tungsten layer 6, the nitride layer is patterned so as to form a gate hard mask 7 defining a gate region. Then, the tungsten layer 6, the tungsten nitride layer 5, the polysilicon layer 4 and the gate insulation layer 3 are sequentially etched by using the gate hard mask 7 as an etching barrier, so as to form a tungsten gate 8.
Although not shown, a gate re-oxidation step is performed for the resultant of the semiconductor device on which the tungsten gate 8 is formed, thereby recovering etching damages. Next, a series of known succeeding steps of forming a Lightly Doped Drain region (LDD region), forming a gate spacer, and forming a junction region are sequentially carried out so as to manufacture the semiconductor device with the tungsten gate.
However, the conventional method of manufacturing the semiconductor device with the tungsten gate as described above has problems as follows:
First, the gate re-oxidation process is conventionally performed in order to recover the etching damages, after etching the gate. At this time, in the case of performing the typical oxidation process, since abnormal oxidation may be caused at a side surface of the tungsten oxidation layer, a selective oxidation process in which the tungsten layer is not oxidized is carried out instead of the typical oxidation process. Although the selective oxidation process can prevent occurrence of the abnormal oxidation phenomenon at the side surface of the tungsten layer, it cannot prevent the occurrence of defects caused by permeation of oxygen through an interface between the tungsten layer and a polysilicon layer.
Further, in the case of the existing tungsten silicide gate, no deterioration of the characteristics of the gate caused by stress of the nitride layer for the hard mask after etching the gate has been found. However, in the case of the tungsten gate, a stress induced leakage current and an interface trap density caused by the stress of the nitride layer for the hard mask are increasing. These phenomena occur when the stress of the nitride layer for the hard mask is transferred to the tungsten layer, because the tungsten makes a direct effect on the gate insulation layer in the state that the stress applied to the tungsten is insufficiently relaxed due to its characteristic. As a result, voids are generated between the gate insulation layer and the polysilicon layer. To the end, the voids cause the deterioration of the characteristics of the gate.
Therefore, in order to develop the high speed device products, it is possible to realize the semiconductor device to which the tungsten gate is applied so that the aforementioned two problems must be solved.